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? semiconductor components industries, llc, 2014 june, 2014 ? rev. 10 1 publication order number: noil2sm1300a/d noil2sm1300a lupa1300-2: high speed cmos image sensor features ? 1280 x 1024 active pixels ? 14 m x 14 m square pixels ? 1.4? optical format ? monochrome or color digital output ? 500 fps frame rate ? on-chip 10-bit adcs ? 12 lvds serial outputs ? random programmable roi readout ? pipelined and triggered global shutter ? on-chip column fpn correction ? serial peripheral interface (spi) ? limited supplies: nominal 2.5 v and 3.3 v ? ? 50 c to +85 c operational temperature range ? 168-pin pga package ? power dissipation: 1350 mw ? these devices are pb ? free and are rohs compliant applications ? high speed machine vision ? motion analysis ? medical imaging ? intelligent traffic system ? industrial imaging description the lupa1300-2 is an integrated sxga high speed, high sensitivity cmos image sensor. this sensor targets high speed machine vision and industrial monitoring applications. the lupa1300-2 sensor runs at 500 fps and has triggered and pipelined shutter modes. it packs 24 parallel 10-bit a/d converters with an aggregate conversion rate of 740 msps. on-chip digital column fpn correction enables the sensor to output ready to use image data for most applications. to enable simple and reliable system integration, the 12 channels, 1 sync channel, 8 gbps, and lvds serial link protocol supports skew correction and serial link integrity monitoring. the peak responsivity of the 14 m x 14 m 6t pixel is 63 dn/nj/cm 2 . dynamic range is measured at 57 db. in full frame video mode, the sensor consumes 1350 mw from the 2.5 v and 3.3 v power supplies. the sensors integrate a/d conversion, on-chip timing for a wide range of operating modes, and has an lvds interface for easy system integration. by removing the visually disturbing column patterned noise, this sensor enables building a camera without any offline correction or the need for memory. in addition, the on-chip column fpn correction is more reliable than an offline correction, because it compensates for supply and temperature variations. the sensor requires one master clock for operations up to 500 fps. the lupa1300-2 is housed in a 168 pin pga package and is available in a monochrome version and bayer (rgb) patterned color filter array. the monochrome version is also available without glass. contact your local on semiconductor office. http://onsemi.com figure 1. lupa1300 ? 2 die photo
noil2sm1300a http://onsemi.com 2 ordering information marketing part number description package noil2sm1300a-gdc mono with glass 168 pin pga NOIL2SM1300A-GWC mono without glass noil2sc1300a-gdc color with glass ordering code definition opto l2: lupa family m = mono c = color temperature range n o l2 a 1300 m sd g ? c s: standard process 1300: 1.3 megapixel resolution additional functionality d = d263 glass, w = windowless i image sensors on semiconductor package g = cpga product package mark figure 2. marking diagram xxxxx = specific device code a = assembly location wl = wafer lot yy = year ww = work week nnnn = serial number line 1: noil2s x 1300a ? g y c where x denotes m = mono and c = color; y denotes d = d263 glass and w = windowless. line 2: awlyyww where awl is production lot traceability, yyww is the 4 ? digit date code
noil2sm1300a http://onsemi.com 3 specifications key specifications table 1. general specifications parameter specifications active pixels 1280 (h) x 1024 (v) pixel size 14 m x 14 m pixel type 6t pixel architecture pixel rate 630 mbps per channel (12 serial lvds outputs) shutter type pipelined and triggered global shutter frame rate 500 fps at 1.3 mpixel (boosted by subsampling and windowing) master clock 315 mhz for 500 fps windowing (roi) randomly programmable roi read out up to four multiple windows read out windowed, flipped, mirrored, and subsampled readout possible adc resolution 10 ? bit, on ? chip extended dynamic range multiple slope (up to 90 db optical dynamic range) table 2. electro ? optical specifications parameter value conversion gain 0.0325 lsb10/e - full well charge 30 ke - responsivity 63 lsb10/nj/cm 2 at 550 nm fill factor 40% parasitic light sensitivity < 1/10,000 dark noise 1.2025 lsb10 qe x ff 35% at 550 nm fpn 2% rms of the output swing prnu < 1% rms of the output signal dark signal 162 lsb10/s, 5000 e - /s power dissipation 1350 mw absolute maximum ratings table 3. absolute maximum ratings (note 1) ????????? ????????? symbol ??????????????? ??????????????? ???? ???? ????? ????? ???? ???? ????????? ????????? abs (2.5 v supply group) ??????????????? ??????????????? ???? ???? ? 0.5 ????? ????? ???? ???? ????????? ????????? ??????????????? ??????????????? ???? ???? ? 0.5 ????? ????? ???? ???? ????????? ????????? ??????????????? ??????????????? ???? ???? ? 0.5 ????? ????? ???? ???? ????????? ????????? ????????? ??????????????? ??????????????? ???? ???? ????? ????? ???? ???? ??????????????? ??????????????? ???? ???? ????? ????? ???? ???? ????????? ????????? ??????????????? ??????????????? ???? ???? ????? ????? ???? ???? ????????? ????????? ????????? ??????????????? ??????????????? ???? ???? ? 40 ????? ????? ???? ???? c ??????????????? ??????????????? c ???? ???? ????? ????? ???? ???? ????????????????????????????????? ????????????????????????????????? recommended operating ratings ????????? ????????? t j (notes 2 and 5) ??????????????? ??????????????? ???? ???? ? 50 ????? ????? ???? ???? c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. absolute maximum ratings are limits beyond which damage may occur. 2. operating ratings are conditions at which operation of the device is intended to be functional. 3. on semiconductor recommends that our customers become familiar with, and follow the procedures in jedec standard jesd625 ? a. refer to application note an52561. long term exposure toward the maximum storage temperature will accelerate color filter degra dation. 4. caution needs to be taken to a void dried stains on the underside of the glass due to condensation. the glass lid glue is permeable and can absorb moisture if the sensor is placed in a high % rh environment. 5. hts ? high t emperature storage was successfully completed on lup a 1300-2 color devices at +150 c for 500 hours. t emperature cycling was successfully completed from ? 40 c to +125 c up to 1000 cycles. no reliability stress has been performed at ? 50 c.
noil2sm1300a http://onsemi.com 4 electrical specifications table 4. power supply ratings (notes 1, 2 and 3) boldface limits apply for t j = t min to t max , all other limits t j = +30 c. clock = 315 mhz symbol power supply parameter condition min typ max units v ana , gnd ana analog supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux = 0 7 20 ma peak current clock enabled, lux = 0 16 ma standby current shutdown mode, lux = 0 1 ma v dig , gnd dig digital supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux = 0 80 120 ma peak current clock enabled, lux = 0 130 standby current shutdown mode, lux = 0 52 ma v pix, gnd pix pixel supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux = 0 6 50 ma peak current during fot clock enabled, lux = 0, transient duration = 9 s 1.4 a peak current during rot clock enabled, lux = 0, transient duration = 2.5 s 35 ma standby current shutdown mode, lux = 0 1 ma v lvds , gnd lvds lvds supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux = 0 220 275 ma peak current clock enabled, lux = 0 280 ma standby current shutdown mode, lux = 0 100 ma v adc , gnd adc adc supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux = 0 210 275 ma peak current clock enabled, lux = 0 260 ma standby current shutdown mode, lux = 0 3 ma v buf , gnd buf buffer supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux = 0 30 50 ma peak current clock enabled, lux = 0 85 ma standby current shutdown mode, lux = 0 0.1 ma v sample , gnd sample sampling circuitry supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux = 0 2 ma peak current clock enabled, lux = 0 42 ma standby current shutdown mode, lux = 0 1 ma v res reset supply operating voltage -5% 3.5 +5% v dynamic current clock enabled, lux = 0 2 15 ma peak current clock enabled, lux = 0 65 ma standby current shutdown mode, lux = 0 2 ma 1. all parameters are characterized for dc conditions after thermal equilibrium is established. 2. the peak currents were measured without the load capacitor from the ldo (low dropout regulator). the 100 nf capacitor bank wa s connected to the pin in question. 3. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to thi s high ? impedance circuit. 4. the vres_ab and vprech power supply should be designed to have a sourcing and sinking current capability for frame rates of the order of 20k frames /sec.
noil2sm1300a http://onsemi.com 5 table 4. power supply ratings (notes 1, 2 and 3) boldface limits apply for t j = t min to t max , all other limits t j = +30 c. clock = 315 mhz symbol units max typ min condition parameter power supply v res_ab (note 4) antiblooming supply operating voltage -10% 0.7 +10% v dynamic current clock enabled, lux = 0 1 ma peak current following edge reset clock enabled, lux = 0 50 ma standby current shutdown mode, lux = 0 1 ma v res_ds reset dual slope supply operating voltage 1.8 2.5 3.675 v dynamic current clock enabled, lux = 0 0.4 3 ma peak current clock enabled, lux = 0 36 ma v res_ts reset triple slope supply operating voltage 1.8 2.2 3.675 v dynamic current clock enabled, lux = 0 0.3 2 ma peak current clock enabled, lux = 0 14 ma v mem_l memory element low level supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux = 0 0.2 1 ma peak current during fot clock enabled, lux = 0 62 ma peak current during fot clock enabled, bright 30 ma v mem_h memory element high level supply operating voltage -5% 3.3 +5% v dynamic current clock enabled, lux = 0 1 ma peak current during fot clock enabled, lux = 0 45 ma v prech (note 4) pre_charge driver supply operating voltage -10% 0.7 +10% v dynamic current clock enabled, lux = 0 0.3 3 ma peak current during fot clock enabled, lux = 0 32 ma peak current during fot clock enabled, lux = bright 25 ma 1. all parameters are characterized for dc conditions after thermal equilibrium is established. 2. the peak currents were measured without the load capacitor from the ldo (low dropout regulator). the 100 nf capacitor bank wa s connected to the pin in question. 3. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to thi s high ? impedance circuit. 4. the vres_ab and vprech power supply should be designed to have a sourcing and sinking current capability for frame rates of the order of 20k frames /sec. every module in the image sensor has its own power supply and ground. the grounds can be combined externally, but not all power supply inputs may be combined. some power supplies must be isolated to reduce electrical crosstalk and improve shielding, dynamic range, and output swing. internal to the image sensor, the ground lines of each module are kept separate to improve shielding and electrical crosstalk between them. the lupa1300-2 contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, take normal precautions to avoid voltages higher than the maximum rated voltages in this high impedance circuit. unused inputs must always be tied to an appropriate logic level, for example, v dd or gnd. all cap_xxx pins must be connected to ground through a 100 nf capacitor. the recommended combinations of supplies are: ? analog group of +2.5 v supply: v sample , v res_ds , v mem_l , v adc , v pix , v ana , v buf ? digital group of +2.5 v supply: v dig , v lvds ? combine v prech and v res_ab to one supply (note 4) table 5. power dissipation (note 1) power supply specifications according to table 4. symbol parameter condition typ units power stdby standby power blocks in standby with spi upload 400 mw power average power dissipation lux = 0, clock = 315 mhz, 500 fps 1350 mw
noil2sm1300a http://onsemi.com 6 table 6. ac electrical characteristics (note 1) the following specifications apply for vdd = 2.5 v, clock = 315 mhz, 500 fps. symbol parameter condition typ max units f clk input clock frequency fps = 500 315 mhz dc clk clock duty cycle at maximum clock 50 % dcd duty cycle distortion at maximum clock 250 ps jitter peak-to-peak 50 ps fps frame rate maximum clock speed 500 fps note: duty cycle distortion and jitter is passed directly from input to output. therefore, dcd and jitter tolerance depends on t he customer?s system clock generation circuitry. overview this data sheet describes the interface of the lup a1300-2 image sensor. the sxga resolution cmos active pixel sensor features synchronous shutter and a maximal frame rate of 500 fps in full resolution. the readout speed is boosted by sub sampling and the windowed region of interest (roi) readout. fpn correction cannot be used in conjunction with sub-sampling and windowed region of interest readout for windows starting with non zero kernel address. high dynamic range scenes can be captured using the double and multiple slope functionality. user programmable row and column start and stop positions enables windowing. sub sampling reduces resolution while maintaining the constant field of view and an increased frame rate. the lupa1300-2 sensor has 12 lvds high speed outputs that transfer image data over longer distances. this simplifies the surrounding system. the lvds interface can receive high speed and wide bandwidth data signals and maintain low noise and distortion. a special training mode enables the receiving system to synchronize the incoming data stream when switching to master, slave, or triggered mode. the image sensor also integrates a programmable offset and gain amplifier for each channel. a 10-bit adc converts the analog signal to a 10-bit digital word stream. the sensor uses a 3-wire serial peripheral interface (spi). it requires only one master clock for operation up to 500 fps. the sensor is available in a monochrome version or bayer (rgb) patterned color filter array. it is placed in a 168-pin ceramic pga package. figure 2 depicts the photovoltaic response of the lupa1300 ? 2. figure 3 shows the spectral response for the mono and color versions of lupa1300-2. photovoltaic response curve figure 3. photovoltaic response of lupa1300 ? 2
noil2sm1300a http://onsemi.com 7 spectral response curve 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 400 wavel ength (nm ) r g1 g2 b m spectral response a/w figure 4. spectral response of lupa1300 ? 2 mono and color 500 600 700 800 900 1000 color filter array the color version of lupa1300-2 is available in bayer (rgb) patterned color filter array. the orientation of rgb is shown in figure 4. figure 5. rgb bayer r (0,1) g (0,0) g (1,1) b (1,0) x_readout direction y_readout direction top view lupa 1300 ? 2 pixel array
noil2sm1300a http://onsemi.com 8 sensor architecture image sensor core the floor plan of the architecture is shown in figure 5. the sensor consists of a pixel array, analog front end, data block, and lvds transmitters and receivers. separate modules for the spi, clock division, and sequencer are also integrated. the image sensor of 1280 x 1024 active pixels is read out in progressive scan. this architecture enables programmable addressing in the x-direction in steps of 24 pixels, and in the y-direction in steps of one pixel. the starting point of the address can be uploaded by the spi. the afe prepares the signal for the digital data block when the data is multiplexed and prepared for the lvds interface. figure 6. floor plan of the sensor pixel array (1280x1024) analog front end (afe) data formatting lvds interface tx and rx clk_in 12 x lvds outputs at 630 msps 28 analog channels, 31.5 msps 12 x 10 ? bit digital channels, 63 msps sequencer & logic clk_out clock divider 24 x 10 ? bit digital channels, 31.5 msps 31.5 mhz 63 mhz 315 mhz spi clk x & clk y local registers the 6t pixel to obtain the global shutter feature combined with a high sensitivity and good parasitic light sensitivity (pls), implement the pixel architecture shown in figure 6. this pixel architecture is designed with a 14 m x 14 m pixel pitch to meet the specifications listed in t able 1 and t able 2 on page 3. this architecture also enables pipelined or triggered mode. figure 7. 6t pixel architecture vpix vmem reset sample select
noil2sm1300a http://onsemi.com 9 analog front end programmable gain amplifiers the pgas amplify the signal before sending it to the adcs. the amplification inside the pga is controlled by one spi setting: afemode [5:3]. six gain steps can be selected by the afemode<5:3> register. table 7 lists the six gain settings. the unity gain selection of the pga is done by the default afemode<5:3> setting. table 7. gain settings afemode<5:3> gain 000 1 001 1.5 010 2 011 2.25 100 3 101 4 analog to digital converter the sensor has 24 10-bit pipelined adcs on board. the adcs nominally operate at 31.5 msamples/s. table 8. adc parameters parameter specification data rate 31.5 msamples/s quantization 10 bit dnl typ. < 1 dn inl typ. < 1 dn data block the data block is positioned in between the analog front end (output stage + adcs) and the lvds interface. it muxes the outputs of two adcs to one lvds block and performs some minor data handling: ? crc calculation and insertion ? training and test pattern generation it also contains a huge part of the functionality for black level calibration and fpn correction. a number of data blocks are placed in parallel to serve all data output channels. one additional channel generates the synchronization protocol. a high level overview is illustrated in the following figure. figure 8. data block
noil2sm1300a http://onsemi.com 10 lvds block the lvds block is positioned below the data block. it receives a differential clock signal, transmits differential data over the 12 data channels, and transmits a lvds clock signal and a synchronization signal over the clock and synchronization channel. a number of lvds transmitter blocks are placed in parallel to serve all data, clock, and synchronization output channels. a high level overview is illustrated in the following figure. figure 9. lvds block ? high level overview lvds se rialize r<0 > serializer <11> serializer <1> cloc kge nerato r se rializer serializer lvds se rialize r<0 > serializer <11> serializer <1> cloc kge nerato r se rializer se rializer serializer serializer lvds transmitter clock lvds transmitter <0> lvds transmitter <1> lvds transmitter <11> lvds transmitter synch lvds receiver the function of this block is to take 10 bits of the protocol block, serialize these bits, and converts them to an lvds standard (tia/eia 644a) compatible differential output signal. the block must also provide a clock to the host, to allow data recovery. this clock is an on-chip version of the clock coming from the host. sequencer and logic the sequencer generates the complete internal timing of the pixel array and the readout. the timing can be controlled by the user through the spi register settings. the sequencer operates on the same clock as the data block. this is a division by 10 of the input clock (internally divided). table 9 lists the internal registers. these registers are discussed in detail in detailed description of internal registers on page 15. table 9. internal registers block register name address [6..0] field reset value description mbs (reserved) fix1 0 [7:0] 0x00 reserved, fixed value fix2 1 [7:0] 0xff reserved, fixed value fix3 2 [7:0] 0x00 reserved, fixed value fix4 3 [7:0] 0x00 reserved, fixed value fix5 4 [7:0] 0x08 reserved, fixed value lvds clk divider lvdsmain 5 [3:0] ?0110? lvds trim [7:4] 0 clkadc phase lvdspwd1 6 [7:0] 0x00 power down channel 7:0 lvdspwd2 7 [5:0] 0 power down channel 13:8 [6] 0 power down all channels [7] 0 lvds test mode fix6 8 [7:0] 0x00 reserved, fixed value afe afebias 9 [3:0] ?1000? afe current biasing afemode 10 [2:0] ?111? vrefp, vrefm settings [5:3] ?000? pga settings [6] 0 power down afe afepwd1 11 [7:0] 0x00 power down adc_channel_2x 7 to 0
noil2sm1300a http://onsemi.com 11 table 9. internal registers block description reset value field address [6..0] register name afe afepwd2 12 [3:0] 0x00 power down adc_channel_2x 11 to 8 bias block bandgap 13 [0] ?0? power down bandgap and currents [1] ?1? external resistor [2] ?0? external voltage reference [5:3] ?000? bandgap trimming image core imcmodes 14 [0] 0 power down [1] ?1? enable vrefcol regulator [2] ?1? enable precharge regulator [3] 0 disable internal bias for vprech [4] ?1? disable column load [5] ?0? clkmain invert fix7 15 [7:0] 0x00 reserved, fixed value fix8 16 [7:0] 0x00 reserved, fixed value imcbias1 17 [3:0] ?1000? bias colfpn dac buffer [7:4] ?1000? bias precharge regulator imcbias2 18 [3:0] ?1000? bias pixel precharge level [7:4] ?1000? bias column ota imcbias3 19 [3:0] ?1000? bias column unip fast [7:4] ?1000? bias column unip slow imcbias4 20 [3:0] ?1000? bias column load [7:4] ?1000? bias column precharge data block fix9 21 [7:0] 0x20 reserved, fixed value fix10 22 [7:0] 0xc0 reserved, fixed value dataconfig1 23 [1:0] 0x00 reserved, fixed value [2] 1 ?1?: enables user upload of dacvrefadc register value ?0?: keeps default value [3] 0 enable prbs generation [4] 0 reserved, fixed value [5] 0 reserved, fixed value [7:6] 0x03 training pattern inserted to sync lvds receivers dataconfig2 24 [7:0] 0x2a training pattern inserted to sync lvds receivers fix11 25 [7:0] 0 reserved, fixed value dacvrefadc 26 [7:0] 0x84 input to dac to set the offset at the input of the adc fix12 27 [7:0] 0x80 reserved, fixed value fix13 28 [7:0] reserved, fixed value fix14 29 [7:0] reserved, fixed value datachannel0_1 30 [0] 0 bypass the data block [1] 0 enables the fpn correction [2] 0 overwrite incoming adc data by the data in the testpat register [3] 0 reserved, fixed value [5:4] 0x00 pattern inserted to generate a test image
noil2sm1300a http://onsemi.com 12 table 9. internal registers block description reset value field address [6..0] register name data block datachannel0_2 31 [7:0] 0x00 pattern inserted to generate a test image datachannel1_1 32 [0] 0 bypass the data block [1] 0 enables the fpn correction [2] 0 overwrite incoming adc data by the data in the testpat register [3] 0 reserved, fixed value [5:4] 0x00 pattern inserted to generate a test image datachannel1_2 33 [7:0] 0x00 pattern inserted to generate a test image datachan- nel12_1 54 [0] 0 bypass the data block [1] 0 enables the fpn correction [2] 0 overwrite incoming adc data by the data in the testpat register [3] 0 reserved, fixed value [5:4] 0x00 pattern inserted to generate a test image datachan- nel12_2 55 [7:0] 0x00 pattern inserted to generate a test image sequencer seqmode1 56 [0] 1 enables sequencer for image capture [1] 1 ?1?: master mode, integration timing is generated on-chip ?0?: slave mode, integration timing is controlled off-chip through int_time1, int_time2 and int_time3 pins [2] 0 ?0?: pipelined mode ?1?: triggered mode [3] 0 enables(?1?)/disables(?0?) subsampling [4] 0 ?1?: color subsampling scheme: 1:1:0:0:1:1:0:0 ?0?: b&w subsampling scheme: 1:0:1:0:1 [5] 0 enable dual slope [6] 0 enable triple slope [7] 0 enables continued row select (that is, assert row select during pixel read out) seqmode2 57 [4:0] ?10000? must be overwritten with ?10001? to this register after startup, before readout. [6:5] ?00? number of active windows: ?00?: 1 window ?01?: 2 windows ?10?: 3 windows ?11?: 4 windows seqmode3 58 [0] ?1? enables the generation of the crc10 on the data and sync channels [1] ?0? enable readout black/grey columns [2] ?0? enable column fpn calibration/enable readout dummy line [5:3] ?001? number of frames in nondestructive read out: ?000?: invalid ?001?: one reset, one sample (default mode) ?010?: one reset, two samples ?
noil2sm1300a http://onsemi.com 13 table 9. internal registers block description reset value field address [6..0] register name sequencer [6] 0 controls the granularity of the timer settings (only for those that have ?granularity selectable? in the description): ?0?: expressed in number of lines ?1?: expressed in clock cycles (multiplied by 2**seqmode4[3:0]) [7] 0 allows delaying the syncing of events that happen outside of rot to the next rot. this avoids image artefacts. seqmode4 59 [3:0] 0x00 multiplier factor (=2**seqmode4[3:0]) for the timers when working in clock cycle mode [5:4] 0x0 selects the source signals to put on the digital test pins (monitor pins): ?00?: integration time settings ?01?: eos signals ?10?: frame sync signals ?11?: functional test mode [6] ?0? reverse read out in x direction [7] ?0? reverse read out in y direction window1_1 60 [7:0] 0x00 y start address for window 1 window1_2 61 [1:0] 0x00 y start address for window 1 [7:2] 0x00 x start address for window 1 window1_3 62 [7:0] 0xff y end address for window 1 window1_4 63 [1:0] 0x3 y end address for window 1 [7:2] 0x36 x width for window 1 window2_1 64 [7:0] 0x00 y start address for window 2 window2_2 65 [1:0] 0x00 y start address for window 2 [7:2] 0x00 x start address for window 2 window2_3 66 [7:0] 0xff y end address for window 2 window2_4 67 [1:0] 0x3 y end address for window 2 [7:2] 0x36 x width for window 2 window3_1 68 [7:0] 0x00 y start address for window 3 window3_2 69 [1:0] 0x00 y start address for window 3 [7:2] 0x00 x start address for window 3 window3_3 70 [7:0] 0xff y end address for window 3 window3_4 71 [1:0] 0x3 y end address for window 3 [7:2] 0x36 x width for window 3 window4_1 72 [7:0] 0x00 y start address for window 4 window4_2 73 [1:0] 0x00 y start address for window 4 [7:2] 0x00 x start address for window 4 window4_3 74 [7:0] 0xff y end address for window 4 window4_4 75 [1:0] 0x3 y end address for window 4 [7:2] 0x36 x width for window 4 res_length1 76 [7:0] 0x02 length of pix_rst (granularity selectable) res_length2 77 [7:0] 0x00 length of pix_rst (granularity selectable) res_dsts_length 78 [7:0] 0x01 length of resetds and resetts (granularity selectable) tint_timer1 79 [7:0] 0xff length of integration time (granularity selectable) tint_timer2 80 [7:0] 0x03 length of integration time (granularity selectable)
noil2sm1300a http://onsemi.com 14 table 9. internal registers block description reset value field address [6..0] register name tint_ds_timer1 81 [7:0] 0x40 length of ds integration time (granularity selectable) tint_ds_timer2 82 [1:0] 0x00 length of ds integration time (granularity selectable) tint_ts_timer1 83 [7:0] 0x0c length of ts integration time (granularity selectable) tint_ts_timer2 84 [1:0] 0x00 length of ts integration time (granularity selectable) tint_black_timer 85 [7:0] 0x06 reserved, fixed value rot_timer 86 [7:0] 0x09 length of rot (granularity clock cycles) fot_timer 87 [7:0] 0x3b length of fot (granularity clock cycles) fot_timer 88 [1:0] 0x01 length of fot (granularity clock cycles) prechpix_timer 89 [7:0] 0x7c length of pixel precharge (granularity clock cycles) prechpix_timer 90 [1:0] 0x00 length of pixel precharge (granularity clock cycles) prechcol_timer 91 [7:0] 0x03 length of column precharge (granularity clock cycles) rowselect_timer 92 [7:0] 0x06 length of rowselect (granularity clock cycles) sample_timer 93 [7:0] 0xf8 length of pixel_sample (granularity clock cycles) sample_timer 94 [1:0] 0x00 length of pixel_sample (granularity clock cycles) vmem_timer 95 [7:0] 0x10 length of pixel_vmem (granularity clock cycles) vmem_timer 96 [1:0] 0x01 length of pixel_vmem (granularity clock cycles) delayed_rdt_tim- er 97 [7:0] 0 readout delay for testing purposes (granularity selectable) delayed_rdt_tim- er 98 [7:0] 0 readout delay for testing purposes (granularity selectable) fix29 99 [0] 0 reserved, fixed value fix30 100 [0] 0 reserved, fixed value fix31 101 [0] 0 reserved, fixed value fix32 102 [0] 0 reserved, fixed value fix33 103 [0] 0 reserved, fixed value fix34 104 [0] 0 reserved, fixed value detailed description of internal registers the registers must be changed only during idle mode, that is, when seqmode1[0] is ?0?. uploaded registers have an immediate effect on how the frame is read out. parameters uploaded during readout may have an undesired effect on the data coming out of the images. mbs block the register block contains registers for sensor testing and debugging. all registers in this block must remain unchanged after startup. lvds clock divider block this block controls division of the input clock for the lvds transmitters or receivers. this block also enables shutting down one or all lvds channels. for normal operation, this register block must remain untouched after startup. afe block this register block contains registers to shut down adc channels or the complete afe block. this block also contains the register for setting the pga gain: afe_mode[5:3]. refer to absolute maximum ratings on page 3 for more details on the pga settings. biasing block this block contains several registers for setting biasing currents for the sensor. default values after startup must remain unchanged for normal operation of the sensor. image core block the registers in this block have an impact on the pixel array itself. default settings after startup must remain unchanged for normal operation of the image sensor.
noil2sm1300a http://onsemi.com 15 data block the data block is positioned in between the analog front end (output stage + adcs) and the lvds interface. it muxes the outputs of 2 adcs to one lvds block and performs some minor data handling: ? crc calculation and insertion. all data can be protected by a 10-bit checksum. the crc10 is calculated over all pixels between a line start and a line end. it is inserted in the data stream after the line is completed, if input seq_data_crc is enabled.the polynomial used is (x^10+x^9+x^6+x^3+x^2+x+1) and 10 bits are calculated in parallel. when a new line is started, the seed is the first pixel value of a line. no crc is calculated for that value. from then on, every incoming pixel is updated through the regular crc. ? training and test pattern generation the most important registers in this block are: dataconfig. the dataconfig1[7:6] and dataconfig2[7:0] registers insert a training pattern in the lvds channels to sync the lvds receivers. datachannels. datachannelx_1 and datachannelx_2 (with x=0 to 12) are registers that allow you to enable or disable the fpn correction (datachannelx_1[1]), and generate a test pattern if necessary (datachannelx_1[5:4] and datachannelx_2[7:0]). sequencer block the sequencer block group registers allow enabling or disabling image sensor features that are driven by the onboard sequencer. this block consists of the following registers: seqmode1. the seqmode1 registers have the following subregisters: seqmode1[0]: enables sequencer for image capture, must be ?1? during image acquisition. seqmode1[1]: this subregister has two modes: ?1?: in this default mode the integration timing is generated on-chip. ?0?: in this slave mode, the integration timing must be generated through the int_time1, int_time2, and int_time3 pins. seqmode1[2]: this bit enables pipelined (0) or triggered (1) mode. seqmode1[3]: enable (1) or disable (0) subsampling. seqmode1[4]: this bit sets the type of subsampling scheme used when subsampling is enabled. ?1?: color (1:1:0:0:1:1:0:0:1 ? ) ?0?: black and white (1:0:1:0:1) seqmode1[5]: this bit enables or disables the dual slope integration. seqmode1[6]: this bit enables or disables the triple slope integration. seqmode2. the seqmode2 register consists of only two subregisters: seqmode2[4:0]: default value after startup is ?10000?, but this must be overwritten with the new value ?10001? immediately after startup. seqmode3[6:5]: these two bits set the number of active windows: ?00?: 1 window ?01?: 2 windows ?10?: 3 windows ?11?: 4 windows (max) seqmode3. the seqmode3 register consists of the following subregisters: seqmode3[0]: this bit enables or disables the crc10 generation on the data and sync channels seqmode3[1]: not applicable seqmode3[2]: enables or disables column fpn correction seqmode3[5:3]: enables or disables, and sets the number of frames grabbed in nondestructive readout mode. ?000?: invalid ?001?: default, 1 reset, 1 sample ?010?: 1reset, 2 samples ?011?: 1 reset, 3 samples seqmode3[6]: controls the granularity of the timer settings (only for those that have ?granularity selectable? in the description). as a result, all timer settings are set either in number of applied clock cycles, or in the number of ?readout lines?. ?0?: expressed in number of lines ?1?: expressed in clock cycles (multiplied by 2**seqmode4 [3:0]) seqmode3[7]: allows syncing of events that happen outside of rot to be delayed to the next rot to avoid image artifacts. seqmode4. this register consists of four subregisters: seqmode4[3:0]: multiplier factor (2**seqmode4[3:0]) for the timers when working in clock cycle mode. seqmode4[5:4]: selects the source signals to be put on the digital test pins (monitor1, monitor2, and monitor3 pins) ?00?: integration time settings ?01?: eos signals ?10?: frame sync signals ?11?: functional test mode seqmode4[6]: enables (1) and disables (0) reverse x read out. seqmode4[7]: enables (1) and disables (0) reverse y read out. y1_start (60 and 61, 10 bit). these registers set the y start address for window 1 (default window). x1_start (61, 6bit). this register sets the x start address for window 1 (default window). y1_end (62 and 63, 10 bit). these registers set the y end address for window 1 (default window). x1_kernels (63, 6 bit). this register sets the number of kernels or x width to be read out for window 1 (default window).
noil2sm1300a http://onsemi.com 16 y2_start (64 and 65, 10 bit). these registers set the y start address for window 2 (if enabled). x2_start (65, 6bit). this register sets the x start address for window 2 (if enabled). y2_end (66 and 67, 10 bit). these registers set the y end address for window 2 (if enabled). x2_kernels (67, 6 bit). this register sets the number of kernels or x width to be read out for window 2 (if enabled). y3_start (68 and 69, 10 bit). these registers set the y start address for window 3 (if enabled). x3_start (69, 6bit). this register sets the x start address for window 3 (if enabled). y3_end (70 and 71, 10 bit). these registers set the y end address for window 3 (if enabled). x3_kernels (71, 6 bit). this register sets the number of kernels or x width to be read out for window 3 (if enabled). y4_start (72 and 73, 10 bit). these registers set the y start address for window 4 (if enabled). x4_start (73, 6bit). this register sets the x start address for window 4 (if enabled). y4_end (74 and 75, 10 bit). these registers set the y end address for window 4 (if enabled). x4_kernels (75, 6 bit). this register sets the number of kernels or x width to be read out for window 4 (if enabled). res_length (76 and 77). this register sets the length of the internal pixel array reset (how long are all pixel reset simultaneously). this value is expressed in ?number of lines? or in clock cycles (depends on seqmode3[6]). res_dsts_length. this register sets the length of the internal dual and triple slope reset pulses when enabled. this value is expressed in ?number of lines? or in clock cycles (depends on seqmode3[6]). tint_timer (79 and 80). this register sets the length of the integration time. this value is expressed in ?number of lines? or in clock cycles (depends on seqmode3[6]). tint_ds_timer (81 and 82). this register sets the length of the dual slope integration time. this value is expressed in ?number of lines? or in clock cycles (depends on seqmode3[6]). tint_ts_timer (83 and 84). this register sets the length of the triple slope integration time. this value is expressed in ?number of lines? or in clock cycles (depends on seqmode3[6]). serial peripheral interface (spi) the serial 4-wire interface (or spi) uses a serial input or output to shift the data in or out the register buffer. the chip?s configuration registers are accessed from the outside world through the spi protocol. a 4-wire bus runs over the chip and connects the spi i/os with the internal register blocks. to upload the sensor, follow this sequence: disable sequencer upload sensor for new setting enable sequencer when sequencer is disabled, the training pattern appears on all the channels, including the sync. the interface consists of: ? cs_n: chip select, when low the chip is selected ? clk: the spi clock ? in: master out, slave in, the serial input of the register ? out: master in, slave out, the serial output of the register spi protocol the information on the data ?in? line is: ? a command bit c, indicating a write (?1?) or a read (?0?) access ? 7-bit address ? 8-bit data word (in case of a write access) the data ?out? line is generally in high z mode, except when a read request is performed. data is always written on the bus on the falling edge of the clock, and sampled on the rising edge, as seen in figure 9 and figure 10. this is valid for both the ?in? and ?out? bus. the system clock must be active to keep the spi uploads stored on the chip. the spi clock speed must be slower by a factor of 30 when compared to the system clock (315 mhz nominal speed). figure 10. write access (c = ?1?) the ?out? line is held to high z. the data for the address a is transferred from the shift register to the active register bank (that is, sampled) on a rising edge of cs_n. only the register block with address a can write its data on the ?out? bus. the data on ?in? is ignored. figure 11. read access (c = ?0?)
noil2sm1300a http://onsemi.com 17 image sensor timing and readout frame rate and windowing frame rate the frame rate depends on the input clock, the frame overhead time (fot), and the row overhead time (rot). the frame period is calculated as follows: 1 kernel = 24 pixels = 2 timeslots = 2 granularity clock cycles table 10. frame rate parameters parameter comment clarification fot frame overhead time programmable: default 315 granularity clock cycles (5 s at 63 mhz) rot row overhead time programmable: default 9 granularity clock cycles (143.1 ns at 63 mhz) nr. lines number of lines read out each frame number of lines in roi nr. pixels number of pixels read out each line number of pixels in roi clock period 1/63 mhz = 15.9 ns every channel works at 63 mhz 12 channels result in 756 mhz data rate note: for more information on fps calculation, refer the on semiconductor application note an57864. in global shutter mode, the whole pixel array is integrated simultaneously including the dummy line for fpn correction. figure 12. timing diagram windowing windowing is easily achieved by spi. the starting point of the x and y address and the window size can be uploaded. the minimum step size in the x-direction is 24 pixels (choose only multiples of 24 as start or stop addresses). the minimum step size in the y-direction is one line (every line can be addressed) in normal mode, and two lines in sub sampling mode. the section sequencer and logic on page 11 discusses the use of registers to achieve the desired roi. table 11. typical frame rates at 315 mhz image resolution (x*y) frame read out time (ms) frame rate (fps) 1296 x 1024 1.9760 506 1008 x 1000 1.5807 633 816 x 600 0.7997 1250 648 x 480 0.5370 1862 528 x 512 0.4887 2046 264 x 256 0.1596 6266 144 x 128 0.0640 15625 24 x 2 0.0098 102249
noil2sm1300a http://onsemi.com 18 operation and signaling digital signals depending on the operation mode (master or slave), the pixel array of the image sensor requires different digital control signals. the function of each signal is listed in this table. table 12. overview of digital signals signal name i/o comments monitor_1 output output pin for integration timing, high during integration monitor_2 output output pin for dual slope integration timing, high during integration monitor_3 output output pin for triple slope integration timing, high during integration int_time_3 input integration pin triple slope int_time_2 input integration pin dual slope int_time_1 input integration pin first slope reset_n input sequencer reset, active low clk input system clock (315 mhz) spi_cs input spi chip select spi_clk input clock of the spi (< sensor clock/30) spi_in input data line of the spi, serial input spi_out output data line of the spi, serial output global shutter in a global shutter, light integration occurs on all pixels in parallel, although subsequent readout is sequential. figure 12 shows the integration and readout sequence for the global shutter. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously, and after the integration time, all pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and readout cycle can occur in parallel (refer to pipelined shutter on page 20) or in sequential (refer to triggered shutter on page 22) mode. figure 13. global shutter operation time axis line number integration time b urs t re ad out co mmon rese t common sa mp le &hold flash could occur here
noil2sm1300a http://onsemi.com 19 the timing of the sensor consists of two parts. the first part is related to the exposure time and the control of the pixel. the second part is related to the read out of the image sensor. integration and readout are in parallel or triggered. in the first case, the integration time of frame i is ongoing during the readout of frame i-1. figure 13 shows this parallel timing structure. the readout of every frame starts with a fot, during which the analog value on the pixel diode is transferred to the pixel memory element. after this fot, the sensor is read out line by line. the read out of every line starts with a rot, during which the pixel value is put on the column lines. then the pixels are selected in groups of 24 (12 on rising edge, and 12 on the falling edge of the internal clock). so in total, 54 kernels of 24 pixels are read out every line. the internal timing is generated by the sequencer. the sequencer can operate in two modes: master mode and slave mode. in master mode, all internal timing is controlled by the sequencer, based on the spi settings. in slave mode, the integration timing is directly controlled by over three pins, and the readout timing is still controlled by the sequencer. the seqmode1[1] register of the spi selects between the master and slave modes. figure 14. global readout timing (parallel) reset n ex p os u re time n reset n+1 exposure time n+1 readout frame n ? 1 fo t fot readout frame n pipelined shutter integration and readout occur in parallel and are continuous. you only need to start and stop the batch of image captures. integration of frame n is always ongoing during readout of frame n-1. the readout of every frame starts with a fot, during which the analog value on the pixel diode is transferred to the pixel memory element. after this fot, the sensor is read out line by line. the readout of every line starts with a rot, during which the pixel value is put on the column lines. then the pixels are mixed in the correct adcs, processed, and then sent to the lvds output block. you have two options in the pipelined shutter mode. the first option is to program the reset and integration through the configuration interface and let the sequencer handle integration time automatically. this mode is called master mode. the second option is to drive the integration time through an external pin. this mode is called slave mode.
noil2sm1300a http://onsemi.com 20 programming the exposure time in master mode, the exposure time is configured in two distinct methods (controlled by register seqmode3[6]): ? # lines: obvious, changing signals that control integration time. they are always changed during rot to avoid any image artefacts. ? # clock cycles: must be multiplied by (2**seqmode4[3:0]). when the counter expires, changes are put into effect immediately. asserting the configuration signal (seqmode3[7]) forces delaying signal updates until the next rot. table 13 lists the user programmable timer settings and how they are interpreted by the hardware. table 13. user programmable timer settings setting granularity reg_res_length lines/cycles reg_tint_timer lines/cycles reg_tint_ds_timer lines/cycles reg_tint_ts_timer lines/cycles res_dsts_length lines/cycles reg_rot_timer clock cycles reg_fot_timer clock cycles reg_sel_pre_timer clock cycles reg_precharge_timer clock cycles reg_sample_timer clock cycles reg_vmem_timer clock cycles reg_delayed_rdt_timer lines/cycles note that the seqmode3[7] can also be used to sync the user signals in slave mode. the behavior is exactly the same. master mode in master mode the reset and exposure time is written in registers. figure 15. integration and image readout in master mode ensure that the added value of the registers res_length and tint_timer always exceeds the number of lines that are read out. this is because the sequencer samples a new image after integration is complete, without checking if image readout is finished. enlarging res_length to accommodate for this has no impact on image capture.
noil2sm1300a http://onsemi.com 21 slave mode in slave mode, the register values of res_length and tint_timer are ignored. the integration time is controlled by the int_time pin. the relationship between the input pin and the integration time is shown in figure 15. when the input pin int_time is asserted, the pixel array goes out of reset and exposure can begin. when int_time goes low again and the desired exposure time is reached, the image is sampled and read out can begin. figure 16. integration and image readout in slave mode changing pixel?s reset level during line readout might result in image artefacts during a small transient period. as a result, it is advised to only change the value of int_time during rot. triggered shutter the two main differences in the pipelined shutter mode are: ? one single image is read upon every user action. ? integration (and read out) is under control of the user through pin int_time. this means that for every frame, you need to manually intervene. the pixel array is kept in reset state until you assert the int_time input. similar to the pipelined shutter mode, there is a master mode in which the sequencer can control the integration time, or a slave mode in which you can define the integration time. figure 17. integration and readout for triggered shutter fot reset exposure time n reset exposure time n + 1 readout handling rot line readout int_time1 fot readout n fot readout n+1 n+1 fot reset the possible applications for this triggered shutter mode are: ? synchronize external flash with exposure ? apply extremely long integration times (only in slave mode)
noil2sm1300a http://onsemi.com 22 master mode in this mode, a rising edge on int_time1 pin is used to trigger the start of integration and read out. the tint_timer defines the integration time independent of the assertion of the input pin int_time1. after the integration time counter runs out, the fot automatically starts and the image readout is done. during readout, the image array is kept in reset. a request for a new frame is started again when a new rising edge on int_time is detected. the time of the falling edge is not important in this mode. slave mode integration time control is identical to the pipelined shutter slave mode. the int_time1 pin controls the start of integration. when int_time is deasserted, the fot starts (analog value on the pixel diode is transferred to the pixel memory element). only at that time, image read out can start (similar to the pipelined read out). during read out, the image array is kept in reset. a request for a new frame is started when int_time goes high again. non destructive readout (ndr) figure 18. principle of non destructive readout time the sensor can also be read out in a nondestructive method. after a pixel is initially reset, it can be read multiple times, without being reset. you can record the initial reset level and all intermediate signals. high light levels saturate the pixels quickly, but a useful signal is obtained from the early samples. for low light levels, the later or latest samples must be used. essentially, an active pixel array is read multiple times, and reset only once. the external system intelligence interprets the data. table 14 on page 23 summarizes the advantages and disadvantages of nondestructive readout. table 14. advantages and disadvantages of non destructive readout advantages disadvantages low noise, because it is true cds system memory required to record the reset level and the intermediate samples high sensitivity. the conversion capacitance is kept low. requires multiples readings of each pixel, so there is higher data throughput high dynamic range. the results include signals for short and long integration times. requires system level digital calculations note that the amount of samples taken with one initial reset is programmable in the nr_of_ndr_steps register. if nr_of_ndr_steps is one, the sensor operates in the default method, that is one reset and one sample. this is called the disable nondestructive read out mode. when nr_of_ndr_steps is two, there is one reset and two samples, and so on. in the slave mode, nothing changes on the protocol of the signals int_time_*. the sequencer suppresses the internal reset signal to the pixel array.
noil2sm1300a http://onsemi.com 23 image format and read out protocol the active area read out by the sequencer in full frame mode is shown in figure 18. before the actual pixels are read out, one dummy line is read to enable column fpn correction. a reference voltage is applied to the columns and the entire line is read as if real pixel values are placed on the columns. pixels are always read in multiples of 24 (one value to every channel in the afe). the last time slot contains not only valid pixels, but also two dummy columns, six grey columns, and eight black columns. figure 19. sensor read out format
noil2sm1300a http://onsemi.com 24 the following sections discuss the appearance of the output (data and synchronization codes) in several relevant configurations. t welve output channels are connected to the 24 adcs and handle the data. one additional channel contains all the synchronization codes for the receiver. this indicates, for example, the start of a frame, the end of a frame, whether the data channels contain data, crc, a training pattern, and so on. the sequencer provides the synchronization channel with the correct synchronization or protocol signals, as shown in figure 7. the synchronization codes are listed in table 15. note that a fs also serves as ls, and vice versa. table 15. synchronization codes sync code abbreviation 10-bit code frame start fs 0x059 line start ls 0x056 frame end fe 0x05a line end le 0x055 grey/black cols gbc 0x0a9 crc crc 0x0a6 fpn stored values fpn 0x13c normal data d 0x193 training pattern t t this table provides a detailed overview of remapping one full row read out. table 16. remapping scheme for one row timeslot ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 1a 0 2 4 6 8 10 12 14 16 18 20 22 1b 1 3 5 7 9 11 13 15 17 19 21 23 2a 47 45 43 41 39 37 35 33 31 29 27 25 2b 46 44 42 40 38 36 34 32 30 28 26 24 3a 48 50 52 54 56 58 60 62 64 66 68 70 3b 49 51 53 55 57 59 61 63 65 67 69 71 4a 95 93 91 89 87 85 83 81 79 77 75 73 4b 94 92 90 88 86 84 82 80 78 76 74 72 5a 96 98 100 102 104 106 108 110 112 114 116 118 5b 97 99 101 103 105 107 109 111 113 115 117 119 6a 143 141 139 137 135 133 131 129 127 125 123 121 6b 142 140 138 136 134 132 130 128 126 124 122 120 7a 144 146 148 150 152 154 156 158 160 162 164 166 7b 145 147 149 151 153 155 157 159 161 163 165 167 8a 191 189 187 185 183 181 179 177 175 173 171 169 8b 190 188 186 184 182 180 178 176 174 172 170 168 9a 192 194 196 198 200 202 204 206 208 210 212 214 9b 193 195 197 199 201 203 205 207 209 211 213 215 10a 239 237 235 233 231 229 227 225 223 221 219 217 10b 238 236 234 232 230 228 226 224 222 220 218 216 11a 240 242 244 246 248 250 252 254 256 258 260 262 11b 241 243 245 247 249 251 253 255 257 259 261 263 12a 287 285 283 281 279 277 275 273 271 269 267 265 12b 286 284 282 280 278 276 274 272 270 268 266 264 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 53a 1248 1250 1252 1254 1256 1258 1260 1262 1264 1266 1268 1270 53b 1249 1251 1253 1255 1257 1259 1261 1263 1265 1267 1269 1271 54a 1295 1293 1291 1289 1287 1285 1283 1281 1279 1277 1275 1273
noil2sm1300a http://onsemi.com 25 table 16. remapping scheme for one row timeslot ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 54b 1294 1292 1290 1288 1286 1284 1282 1280 1278 1276 1274 1272 crc table 17. remapping scheme for one row in reverse x/y readout mode timeslot ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 54a 1295 1293 1291 1289 1287 1285 1283 1281 1279 1277 1275 1273 54b 1294 1292 1290 1288 1286 1284 1282 1280 1278 1276 1274 1272 53a 1248 1250 1252 1254 1256 1258 1260 1262 1264 1266 1268 1270 53b 1249 1251 1253 1255 1257 1259 1261 1263 1265 1267 1269 1271 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 2a 47 45 43 41 39 37 35 33 31 29 27 25 2b 46 44 42 40 38 36 34 32 30 28 26 24 1a 0 2 4 6 8 10 12 14 16 18 20 22 1b 1 3 5 7 9 11 13 15 17 19 21 23 crc table 18. remapping scheme for one row in color subsampling mode timeslot ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 1a 0 45 4 41 8 37 12 33 16 29 20 25 1b 1 44 5 40 9 36 13 32 17 28 21 24 2a 48 93 52 89 56 85 60 81 64 77 68 73 2b 49 92 53 88 57 84 61 80 65 76 69 72 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 27a 1248 1293 1252 1289 1256 1285 1260 1281 1264 1277 1268 1273 27b 1249 1292 1253 1288 1257 1284 1261 1280 1265 1276 1269 1272 crc table 19. remapping scheme for one row in monochrome subsampling mode timeslot ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 1a 0 2 4 6 8 10 12 14 16 18 20 22 1b 46 44 42 40 38 36 34 32 30 28 26 24 2a 48 50 52 54 56 58 60 62 64 66 68 70 2b 94 92 90 88 86 84 82 80 78 76 74 72 3a 96 98 100 102 104 106 108 110 112 114 116 118 3b 142 140 138 136 134 132 130 128 126 124 122 120 4a 144 146 148 150 152 154 156 158 160 162 164 166 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 27a 1248 1250 1252 1254 1256 1258 1260 1262 1264 1266 1268 1270 27b 1294 1292 1290 1288 1286 1284 1282 1280 1278 1276 1274 1272 crc
noil2sm1300a http://onsemi.com 26 single window mode containing timeslot 54 in this operation mode, only part of the sensor is read out, as shown by the shaded area in figure 19. a clear distinction is made with the single window mode that does not contain the timeslot 54, because the output synchronization protocol is slightly different. figure 20. single window containing timeslot 54 figure 20 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line) for this window mode. figure 21. waveform for single window containing timeslot 54 data channel sync channel sequencer internal state line ys line ye black timeslot x timeslot x+1 53 54 crc t d gb le cr c fot rot rot rot timeslot timeslot timeslot t t t d rot data channel sync channel dd l s d line ys+1
noil2sm1300a http://onsemi.com 27 single window mode not containing timeslot 54 in this operation mode, only part of the sensor is read out, as shown in figure 21. although the window is defined as not containing any data from timeslot 54, it is read out to provide information on grey and black columns to the user. figure 22. single window not containing timeslot 54 figure 22 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line) for this window mode. figure 23. waveform for single window not containing timeslot 54 data channel sequencer internal state line ys ys+1 line ye black timeslot xstart timeslot xend timeslot 54 t t d e gb gb cr c t t fot rot rot rot rot d timeslot xend-1 timeslot dd l s ddl timeslot crc line sync channel note that the dummy black line is read completely. reading out multiple windows does not differ from combining the windowed modes in sections single w indow mode containing timeslot 54 on page 27 and single window mode not containing timeslot 54. the dummy black line again spans the entire width of the sensor and is processed only once, before all configured windows are read. the dummy black line is independent of the window sizes.
noil2sm1300a http://onsemi.com 28 additional features windowing a fully configurable window can be selected for readout. figure 24. window selected for readout p 1024 ixels p 1280 ixels x start y xkernel d y en t star the parameters to configure this window are: x_start. the sensor reads out 24 pixels in one single clock cycle. the granularity of configuring the x start position is also 24. every value written to the windowx_2 register must be multiplied by 24 to find the corresponding column in the pixel array. x_kernels. the number of columns that is read out (x_kernels*24 in full frame mode) in subsampling mode x_kernels*48 represents the number of columns over which subsampling is done. the x_kernels value must be written to the windowx_4 register. y_start. the starting line of the readout window, granularity of 1. note that in subsample mode, the correct y_start position must be uploaded (exact value depends on color or b/w subsampling mode). this value must be written to the windowx_1 and windowx_2 register. y_end. the end line of the readout window, granularity of 1. in all cases (even in reverse scan), y_end are larger than y_start. note that in subsample mode, the correct y_end position must be uploaded (exact value depends on color or b/w subsampling mode). this value must be written to the windowx_3 and windowx_4 register. in case of windowing, the ef fective readout time is smaller than in full frame mode, because only the relevant part of the image array is accessed. as a result, it is possible to achieve higher frame rates. subsampling subsampling reduces resolution while maintaining the constant field of view and an increased frame rate. lupa1300-2 supports monochrome and color subsampling modes of operation. the pixel order for one complete row is shown in table 18 and table 19 on page 26.
noil2sm1300a http://onsemi.com 29 reverse scan reverse scanning is supported in the x and y direction. line 0 (first line on the output) is the top line in normal mode and the bottom line in reverse scanning, as shown in figure 24. as a result, the line numbers always increment. when reverse scanning in x, the operation is analogous. to enable reverse readout in x and y, set the seqmode4[6:7] bits. in addition, the y_start and x_start addresses must be changed to the new starting address. figure 25. normal and reverse scanning in y multiple windows the sequencer supports the readout of four different windows, randomly positioned over the pixel array. the images are read out sequentially. that is, window 1 is read out before window 2, even if both windows show some overlap. next, windows 3 and 4 are read out. each window is treated as a frame and images are read out as shown in figure 26. also, the sum of readout times of all four windows should be less than or equal to the sum of reset time and integration time. (rt w1+rtw2+rtw3+rt w4) < (reset time + integration time). you can configure the number of windows used in the application (one to four). figure 25 shows how to configure two windows spread over the image array. figure 26. multiple windows read from the same pixel array figure 27. readout from windows fot? fs?window1 fe?rot?fs?window 2?fe fotfs window 1ferot fs window 2fe frame 1 frame 2
noil2sm1300a http://onsemi.com 30 figure 27 shows the sequence of integration and read out for multiple windows. the handling of integration time is identical to the single window mode (except that in this case, the maximum integration time is equal to the sum of the y_widths of the two windows). read out starts with a fot that is similar to single window mode. after the fot, all lines of window 1 are read, followed by the lines of window 2. figure 28. exposure and read out of multiple windows fot handling readout handling readout n fot fot rot line readout window 1 line readout window 2 readout n window 2 readout n-1 window 1 readout n-1 2 window 2 window 1 exposure time n reset n+1 exposure time n + 1 reset n fot if the x size of the windows are not identical, the integration time in function of the number of lines read presents multiple slopes (proportional to the x size of these windows). because this can cause confusion when programming the integration time, it is easier to configure all timer registers using the clock cycle configuration instead of the ?line? configuration. multiple slopes dynamic range can be extended by the multiple slope capabilities of the sensor. the four colored lines in figure 28 represent analog signals of the photodiode of four pixels, which decrease as a result of exposure. the slope is determined by the amount of light at each pixel (the more light, the steeper the slope). when the pixels reach the saturation level, the analog does not change despite further exposure. w ithout the multiple slope capabilities, the pixels p3 and p4 are saturated before the end of the exposure time, and no signal is received. however, when using multiple slopes, the analog signal is reset to a second or third reset level (lower than the original) before the integration time ends. the analog signal starts decreasing with the same slope as before, and pixels that were saturated before could be nonsaturated at read out time. for pixels that never reach any of the reset levels (for example, p1 and p2) there is no difference between single and multiple slope operation. by choosing the time stamps of the double and triple slope resets (typical at 90% and 99% of the integration, configurable by the user), it is possible to have a nonsaturated pixel value even for pixels that receive a huge amount of light. figure 29. dynamic range extended by multiple slope capability
noil2sm1300a http://onsemi.com 31 the reset levels are configured through external (power) pins. in master mode, the time stamps of the double and triple slope resets are configured in a method similar to configuring the exposure time. the time stamps are enabled through the registers seqmode1[5] and seqmode1[6], and their values are expressed in line or clock cycles in the registers reg_tint_ds_timer and reg_tint_ts_timer. figure 30. triple slope timing in master mode in slave mode, the values of res_length, tint_timer, tint_ds_timer, and tint_ts_timer in the configuration registers are ignored. you have full control through the pins int_time, int_time_ds, and int_time_ts. you must configure the multiple slope parameters for the application and interpret the pixel data accordingly. figure 31. triple slope timing in slave mode
noil2sm1300a http://onsemi.com 32 column fpn correction the column fpn of the sensor is improved by the offset correction of the columns. at the start of every frame, before read out of the actual lines is done, a fixed voltage is applied at the columns and these values are read out like a real data line. inside the data block, the ?pixel? data for that line is stored in an on-chip fpn memory. when the correction is enabled, the corresponding fpn value is subtracted from the incoming pixel data. this fpn correction must be enabled for every output separately. the registers used to configure the correction are: ? datachannelx_1 with x from 0 to 11. the field [1] of these registers enables the offset corrections of the specific output channel. note: do not change the settings of datachannel12_1. this channel contains synchronization data, not pixel data. if fpn correction is enabled on this channel, the synchronization data becomes corrupt. ? seqmode3. the field[2] must be ?1?. it enables the generation of the line of reference voltages at the columns. figure 31 and figure 32 show the effect of enabling the column fpn correction. these images are magnified up to five times. figure 32. dark image without fpn correction (5x amplified) figure 33. dark image with fpn correction enabled (5x amplified)
noil2sm1300a http://onsemi.com 33 full frame mode in this operation mode, the entire sensor shown in figure 18 on page 24 is read out. figure 33 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line). figure 34. full frame mode readout data channel sync channel data channel sync channel sequencer internal state line 0 line 1 line 1022 line 1023 black timeslot timeslot timeslot 53 timeslot 54 t t fs dd d dd dd gb le cr c t t fot?rot rot rot rot 1 3 2 timeslot crc timeslot figure 35. full frame mode readout with on chip black level calibration disabled data channel sync channel data channel sync channel sequencer internal state line 0 line 1 line 1022 line 1023 black timeslot timeslot timeslot 53 timeslot 54 t t fs dd d dd dd d le cr c t t fot?rot rot rot rot 1 3 2 timeslot crc timeslot off chip automatic black level calibration the last time slot not only contains valid pixels but also two dummy columns, six grey columns, and eight black columns. the grey column values are used to perform off chip black level calibration to maintain a constant black level against any type of drift. these values gauge the response of normal pixels in the dark conditions. grey columns are generated by applying a minimal integration time (black timer register) to the columns. black columns share the same minimal integration time; additionally, the pixels in that column are shielded. grey columns can be used if the integration time is large compared to the minimal integration time. black columns are used if the integration time is in the same order of magnitude as the minimal integration time. the procedure is as follows: 1. decide what digital code should be the desired black level. 0x00 cannot be chosen to avoid underflow in fpn correction. 2. set the sensor to safe settings; dacvrefadc must be on a value that never clips the grey (or black) columns. ? make sure that the grey (or black) columns can be read out without clipping. ? make sure that this is the case for every sensor including dc-shifts due to vt and temperature differences. 3. read-out the grey (or black) columns. 4. calculate the average value of this grey (or black) data; also average it out over the different grey columns. 5. adapt the dacvrefadc if the calculated value deviate from the desired black level value and return to step (2). 6. repeat the procedure for temperature changes.
noil2sm1300a http://onsemi.com 34 package pin list table 20. pin placement layout (top view) 123456789101112131415161718192021222324 a 134 130 127 124 121 118 115 112 109 106 103 100 99 96 93 90 87 84 81 78 75 72 69 65 b * 131 128 125 122 119 116 113 110 107 104 101 98 95 92 89 86 83 80 77 74 71 68 * c 133 132 129 126 123 120 117 114 111 108 105 102 97 94 91 88 85 82 79 76 73 70 67 66 d e f g h j k top view l m n p q r s t 135 139 140 137 145 * 5 7 * 17 19 * * 31 29 * 43 41 * 54 62 60 59 64 u 136 144 141 138 146 * 8 6 * 20 18 * * 30 32 * 42 44 * 53 61 55 58 63 v 149 147 142 * 1 3 9 11 13 15 21 23 25 27 33 35 37 39 45 47 * 52 57 50 w 150 148 143 * 2 4 10 12 14 16 22 24 26 28 34 36 38 40 46 48 * 51 56 49
noil2sm1300a http://onsemi.com 35 table 21. pin list pin no. pin name type direction description position 1 clkoutp lvds o p clk output channel v5 2 clkoutn lvds o n clk output channel w5 3 chp[0] lvds o p output channel [0] v6 4 chn[0] lvds o n output channel [0] w6 5 gndlvds supply i/o lvds ground t7 6 gndadc supply i/o adc ground u8 7 vddadc supply i/o adc power t8 8 vddlvds supply i/o lvds power u7 9 chp[1] lvds o p output channel [1] v7 10 chn[1] lvds o n output channel [1] w7 11 chp[2] lvds o p output channel [2] v8 12 chn[2] lvds o n output channel [2] w8 13 chp[3] lvds o p output channel [3] v9 14 chn[3] lvds o n output channel [3] w9 15 chp[4] lvds o p output channel [4] v10 16 chn[4] lvds o n output channel [4] w10 17 gndlvds supply i/o lvds ground t10 18 gndadc supply i/o adc ground u11 19 vddadc supply i/o adc power t11 20 vddlvds supply i/o lvds power u10 21 chp[5] lvds o p output channel [5] v11 22 chn[5] lvds o n output channel [5] w11 23 chp[6] lvds o p output channel [6] v12 24 chn[6] lvds o n output channel [6] w12 25 chp[7] lvds o p output channel [7] v13 26 chn[7] lvds o n output channel [7] w13 27 chp[8] lvds o p output channel [8] v14 28 chn[8] lvds o n output channel [8] w14 29 gndlvds supply i/o lvds ground t15 30 gndadc supply i/o adc ground u14 31 vddadc supply i/o adc power t14 32 vddlvds supply i/o lvds power u15 33 chp[9] lvds o p output channel [9] v15 34 chn[9] lvds o n output channel [9] w15 35 chp[10] lvds o p output channel [10] v16 36 chn[10] lvds o n output channel [10] w16 37 chp[11] lvds o p output channel [11] v17 38 chn[11] lvds o n output channel [11] w17 39 n/a not assigned v18 40 n/a not assigned w18 41 gndlvds supply i/o lvds ground t18 42 gndadc supply i/o adc ground u17
noil2sm1300a http://onsemi.com 36 table 21. pin list pin no. position description direction type pin name 43 vddadc supply i/o adc power t17 44 vddlvds supply i/o lvds power u18 45 clkinp lvds i lvds input clock 315 mhz p-node v19 46 clkinn lvds i lvds input clock 315 mhz n-node w19 47 syncp lvds o lvds sync and output v20 48 syncn lvds o lvds sync and output w20 49 gnddig supply i/o digital ground w24 50 vdddig supply i/o digital power supply v24 51 cap_vrefm analog o lower limit adc range decoupling w22 52 cap_vrefp analog o higher limit adc range decoupling v22 53 gndadc supply i/o adc ground u20 54 vddadc supply i/o adc power supply t20 55 gnddig supply i/o digital ground u22 56 gndbuf supply i/o column buffers ground w23 57 vddbuf supply i/o column buffers supply v23 58 gndana supply i/o column buffers ground u23 59 vddana supply i/o column buffers supply t23 60 vpix supply i/o pixel core supply t22 61 gndpix supply i/o pixel core ground u21 62 vsamp supply i/o image core select and sample supply t21 63 gndadc supply i/o adc ground u24 64 vdddig supply i/o digital power supply t24 65 nbias_colload analog o column bias decouple a24 66 test_ena cmos i scan pin for sequencer; customer: connect to ground c24 67 int_time1 cmos i integration pin first slope c23 68 int_time2 cmos i integration pin dual slope b23 69 int_time3 cmos i integration pin triple slope a23 70 monitor1 cmos o output pin for integration timing, high during integration c22 71 monitor2 cmos o output pin for dual slope integration timing, high during integration b22 72 monitor3 cmos o output pin for triple slope integration timing, high during integration a22 73 cap_vrefadc analog o adc black reference decoupling c21 74 vpix supply i/o pixel core supply b21 75 cap_vrefcm analog o adc common mode decoupling a21 76 reset_n cmos i/o chip reset (active low) c20 77 scan_en cmos i dft scan enable; customer: connect to ground b20 78 scan_clk cmos i dft clock; customer: connect to ground a20 79 scan_clk_en cmos i dft clock enable; customer: connect to ground c19 80 gndpix supply i/o pixel core ground b19 81 gnddig supply i/o digital ground a19 82 vdddig supply i/o digital power supply c18
noil2sm1300a http://onsemi.com 37 table 21. pin list pin no. position description direction type pin name 83 vpix supply i/o pixel core supply b18 84 pixdiode analog o pixel diode current pin; customer: keep it floating a18 85 gndpix supply i/o pixel core ground c17 86 vsamp supply i/o image core select and sample supply b17 87 vresetab supply i/o anti blooming lower reset level a17 88 vprech supply i/o pixel precharge level/decoupling pin c16 89 vmemh supply i/o pixel memory reference high b16 90 vmeml supply i/o pixel memory reference low a16 91 vreset supply i/o pixel reset level c15 92 vresetds supply i/o pixel dual slope reset level/decoupling pin b15 93 vresetts supply i/o pixel triple slope reset level/decoupling pin a15 94 vresetab supply i/o anti blooming lower reset level c14 95 gndpix supply i/o pixel core ground b14 96 vresetts supply i/o pixel triple slope reset level/decoupling pin a14 97 vresetds supply i/o pixel dual slope reset level/decoupling pin c13 98 vreset supply i/o pixel reset level b13 99 vsamp supply i/o image core select and sample supply a13 100 vmeml supply i/o pixel memory reference low a12 101 vmemh supply i/o pixel memory reference high b12 102 vprech supply i/o pixel precharge level/decoupling pin c12 103 n/a not assigned a11 104 gndpix supply i/o pixel core ground b11 105 vresetab supply i/o anti blooming lower reset level c11 106 vresetts supply i/o pixel triple slope reset level/decoupling pin a10 107 vresetds supply i/o pixel dual slope reset level/decoupling pin b10 108 vreset supply i/o pixel reset level c10 109 vmeml supply i/o pixel memory reference low a9 110 vmemh supply i/o pixel memory reference high b9 111 vprech supply i/o pixel precharge level/decoupling pin c9 112 vresetab supply i/o anti blooming lower reset level a8 113 vsamp supply i/o image core select and sample supply b8 114 gndpix supply i/o pixel core ground c8 115 ibiaspre analog i external current bias for vprech (not connected by default); customer: connect with 0.1 f to ground a7 116 vpix supply i/o pixel core supply b7 117 vdddig supply i/o digital power supply c7 118 gnddig supply i/o digital ground a6 119 gndpix supply i/o pixel core ground b6 120 n/a not assigned c6 121 n/a not assigned a5 122 n/a not assigned b5 123 n/a not assigned c5
noil2sm1300a http://onsemi.com 38 table 21. pin list pin no. position description direction type pin name 124 cap_vrefcm analog o adc common mode decoupling a4 125 vpix supply i/o pixel core supply b4 126 cap_vrefadc analog o adc black reference decoupling c4 127 spics cmos i spi chip select a3 128 spiclk cmos i spi clock b3 129 spiin cmos i spi serial input c3 130 spiout cmos o spi serial output a2 131 mbsbus[0] analog i/o first mixed boundary scan bus; customer: keep it floating b2 132 mbsbus[1] analog i/o second mixed boundary scan bus; customer: keep it floating c2 133 refbg analog i/o external bias resistor; customer: connect with 47 k to ground c1 134 cmdmbs analog i bias current for mbs buffers; customer: connect with 0.1 f to ground a1 135 vdddig supply i/o digital power supply t1 136 gndadc supply i/o adc ground u1 137 vsamp supply i/o image core select and sample supply t4 138 gndpix supply i/o pixel core ground u4 139 vpix supply i/o pixel core supply t2 140 vddana supply i/o analog power supply t3 141 gndana supply i/o analog ground u3 142 vddbuf supply i/o column buffers supply v3 143 gndbuf supply i/o column buffers ground w3 144 gnddig supply i/o digital ground u2 145 vddadc supply i/o adc power supply t5 146 gndadc supply i/o adc ground u5 147 cap_vrefp analog i/o higher limit adc range decoupling v2 148 cap_vrefm analog i/o lower limit adc range decoupling w2 149 vdddig supply i/o digital power supply v1 150 gnddig supply i/o digital ground w1
noil2sm1300a http://onsemi.com 39 table 22. mechanical specifications parameter description min typ max units die (pin 1 is located bottom left) die thickness na 750 na m die position, x offset to the package center na -42 na m die position, y offset to the package center na -150 na m die position, x tilt -1 0 1 deg die position, y tilt -1 0 1 deg die placement accuracy in package -50 0 50 m die rotation accuracy -1 0 1 deg optical center referenced from the die center (x-dir) na -121 na m optical center referenced from the die center (y-dir) na +2280 na m distance from pcb plane to top of the die surface na 1.75 na mm distance from top of the die surface to top of the glass lid na 1.15 na mm glass lid xy size na 27.4 x 27.4 na mm thickness na 0.9 na mm spectral range for optical coating of window 400 - 1100 nm reflection coefficient for window (refer to figure 36) na <0.8 na % mechanical shock jesd22-b104c; condition g na 2000 na g vibration jesd22-b103b; condition 1 20 - 2000 hz mounting profile pb-free wave soldering profile for pin grid array package if no socket is used recommended socket manufacturer andon electronics (www.andonelectronics.com) bga socket: 10-24-05-168-319t-p27-l14 thru hole: 10-24-05-168-347t-p27-l14
noil2sm1300a http://onsemi.com 40 package drawing cpga168, 35.50x30.50 case 107dh ? 01 issue o
noil2sm1300a http://onsemi.com 41 glass lid the lupa1300-2 monochrome and color image sensor uses a glass lid without any coatings. figure 36 shows the transmission characteristics of the glass lid. as shown in figure 36, no infrared attenuating color filter glass is used. a filter must be provided in the optical path when color devices are used (source: http://www.pgo ? online.com). figure 36. transmission characteristics of the glass lid handling precautions for proper handling and storage conditions, refer to the on semiconductor application note an52561. limited warranty on semiconductor?s image sensor business unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to seller?s published specifications and will be free from defects in material and workmanship for two (2) years following the date of shipment. if a defect were to manifest itself within two (2) years period from the sale date, on semiconductor will either replace the product or give credit for the product. return material authorization (rma) on semiconductor packages all of its image sensor products in a clean room environment under strict handling procedures and ships all image sensor products in esd-safe, clean-room-approved shipping containers. products returned to on semiconductor for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product. acceptance criteria specification the product acceptance criteria is available on request. this document contains the criteria to which the lupa1300 ? 2 is tested before being shipped. application note references ? an54468: interfacing the lupa1300-2 with fpga this application note describes the interface between the lupa1300-2 and the fpga, as implemented in the lupa1300-2 demonstration kit. it also provides an overview of the architecture of the demonstration kit and the method used to synchronize channels. ? an54214: high speed layout guidelines for the lupa1300-2 image sensor ? an54598: pixel remapping implementation in lupa1300-2 demonstration kit this application note explains the remapping technique implemented in lup a1300-2 demonstration system to align non consecutive pixels readout to consecutive pixels for creating proper images. it also describes the remapping method during reverse-x/y readout and subsampling modes of operation.
noil2sm1300a http://onsemi.com 42 acronyms acronym description adc analog-to-digital converter afe analog front end bl black pixel data cdm charged device model cds correlated double sampling cmos complementary metal oxide semiconductor crc cyclic redundancy check dac digital-to-analog converter ddr double data rate dnl differential non ? linearity ds double sampling dsnu dark signal non ? uniformity eia electronic industries alliance esd electrostatic discharge fe frame end ff fill factor fot frame overhead time fpga field programmable gate array fpn fixed pattern noise fps frames per second fs frame start hbm human body model img image data (regular pixel data) inl integral non ? linearity acronym description ip intellectual property le line end ls line start lsb least significant bit lvds low-voltage differential signaling msb most significant bit pga programmable gain amplifier pls parasitic light sensitivity prbs pseudo-random binary sequence prnu pixel random non ? uniformity qe quantum efficiency rgb red ? green ? blue rma return material authorization rms root mean square roi region of interest rot row overhead time s/h sample and hold snr signal-to-noise ratio spi serial peripheral interface tia telecommunications industry association t j junction temperature tr training pattern % rh percent relative humidity
noil2sm1300a http://onsemi.com 43 glossary conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. con- version gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. cds correlated double sampling. this is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light. cfa color filter array. the materials deposited on top of pixels that selectively transmit color. dnl differential nonlinearity (for adcs) dsnu dark signal nonuniformity. this parameter characterizes the degree of nonuniformity in dark leakage currents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a photodiode of equal area. in practice, it is never measured. inl integral nonlinearity (for adcs) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. lux photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m 2 = 1/683 w/m 2 ) pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixe l array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response nonuniformity. this parameter characterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and con- verting them into electrons. it is photon wavelength and pixel color dependent. read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. ?soft? reset occurs when the reset transistor is operated below the threshold. ?hard? reset occurs when the reset transistor is operated above threshold. reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel designs, reset noise can be removed with cds. responsivity the standard measure of photodiode performance (regardless of whether it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small subsection; it can be confined to a single color plane. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodiode itself. sensitivity a measure of pixel performance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wavelength. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux is equal to 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterizes the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels.
noil2sm1300a http://onsemi.com 44 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 noil2sm1300a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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